Currently, the mainstream of computer architectures is the von Neumann model. In the von Neumann architecture, its operation is defined by a program made up of sequential instruction streams. The architecture has versatility that enables use for various purposes by changing the program. Not only CPUs (central processing units) playing the central role of computers, but also computing devices for specific purposes such as GPUs (graphics processing units) are configured with the von Neumann architecture, and their basic operation resides in sequential execution of instruction streams.
Up to now, performance improvement of computers has depended on improvement in clock frequencies. Since the fundamentals of the von Neumann architecture are sequential execution of instruction streams, performance improvement can be expected if the instruction execution speed is increased. However, in general-purpose CPUs used in personal computers and servers, the improvement in clock frequencies leveled off at around 3 GHz in the early 2000s. In recent years, measures which realize performance improvement by multicore-based parallel processing have been the mainstream, instead of the clock frequencies, which leveled off.
In the multicore-based parallel processing, performance can be improved by finding out parts that can be executed in parallel from sequential instruction streams (extraction of parallelism) and executing them in parallel. However, it is not easy to extract parallelism from a program in which sequential algorithms are written as instruction streams. As ILP (Instruction Level Parallelism) which extracts parallelism on the instruction level has already reached its limit, parallelism with coarser granularity such as TLP (Thread Level Parallelism) or DLP (Data Level Parallelism) tend to be used recently.
In view of such circumstances, in order to improve the performance of computers in the future, there is a need to shift to intrinsically parallel information processing rather than the processing based on sequential execution of instruction streams as in the conventional technique. To this end, a problem description method suitable for realizing essentially parallel information processing is needed instead of the conventional problem description method based on sequential instruction streams.
One of candidates for this is the Ising model. The Ising model is a model in statistical mechanics for describing the behavior of magnetic bodies and is used for research on magnetic bodies. An Ising model is defined as interactions between sites (spins taking binary values of +1 and −1). It is known that finding a ground state of an Ising model whose topology is a non-planar graph is an NP-hard problem. Since an Ising model expresses a problem by interaction coefficients spread in spatial directions, there is a possibility that information processing using intrinsic parallelism can be realized.
Incidentally, since finding a ground state of an Ising model is an NP-hard problem as described above, solving the problem with a von Neumann computer involves difficulty in terms of computation time. While an algorithm which achieves a higher speed by introducing a heuristic technique has been proposed, calculation method which directly utilizes physical phenomena instead of a von Neumann computer, that is, a method for finding a ground state of an Ising model at a high speed with an analog computer, has been proposed. For example, the device disclosed in PTL 1 is such a device. In such a device, a degree of parallelism corresponding to the problem to be solved is needed. In the case of the Ising model, elements which realize spins and interactions are needed, corresponding to the number of spins in an Ising model whose ground state should be searched for. For example, in the device disclosed in PTL 1, spins and lasers correspond to each other and therefore lasers in the number proportionate to the number of spins are needed. That is, high scalability that can realize a large number of elements is necessary. Therefore, it is desirable that ground state search of an Ising model can be carried out with solid-state elements such as semiconductor devices in which elements as component units can be realized in the state of being arrayed regularly in a large number. Particularly, a structure which is an array structure represented by a memory device such as DRAM or SRAM and in which component units are simple elements so as enhance integration is desirable.